Intelligent parametric scratchap memory architecture

ABSTRACT

An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a U.S. National Stage Application under 35 U.S.C. §371 of PCT Application No. PCT/US2012/072149, filed Dec. 28, 2012, which claims priority under 35 U.S.C. §119(e) from U.S. Provisional Application No. 61/585,176, filed Jan. 10, 2012, the subject matters of which are incorporated herein by reference.

BACKGROUND Field

Embodiments may relate to a single-instruction-multiple data (SIMD) processor and a corresponding memory (or memory subsystems).

BRIEF DESCRIPTION OF THE DRAWINGS

Arrangements and embodiments may be described in detail with reference to the following drawings in which like reference numerals refer to like elements and wherein:

FIG. 1 shows a memory architecture according to an example arrangement;

FIG. 2 shows a two-dimensional 2D array of memory according to an example arrangement;

FIG. 3(a) shows linear interpolation in a scalar way, and FIG. 3(b) shows linear interpolation in a SIMD way;

FIG. 4(a) shows a 2D array of memory, and FIG. 4(b) shows parallel memory banks.

FIG. 5 shows shifted scheme of storing a 2D array in parallel memory banks according to an example embodiment;

FIG. 6 are graphs showing silicon area and maximal power dissipation costs of memory banks configurations of the presented memory subsystem; and

FIG. 7 illustrates trade offs for values of N and Blk_(H);

FIG. 8(a) shows a look-up table data structure, and FIG(b) shows a look-up table stored in 8 memory banks;

FIG. 9 shows four LUTs of 16 values stored in 4 groups of 2 memory banks per group; and

FIG. 10 shows writing a vector of N=8 LUT values to the memory bank.

DETAILED DESCRIPTION

Embodiments may relate to an electronic apparatus that includes a processor and a memory subsystem that includes a plurality of parallel memory banks.

Single-Instruction-Multiple-Data (SIMD) processors may be used to accelerate computationally intensive tasks, such as digital signal processing, multimedia and graphics, by exploiting data level parallelism. SIMD processors (and/or logic) may be throughput-oriented and may contain a set of SIMD functional units (datapath) capable of processing N data elements in parallel rather than one element, such as with scalar processors. To achieve a high throughput of SIMD processing, beside a properly dimensioned datapath, an efficient on-chip memory subsystem may be needed.

FIG. 1 shows a memory architecture according to an example arrangement to enable high SIMD processing throughput. The memory architecture may include a processor 20 having an on-chip memory subsystem 30 and a datapath 40, such as a SIMD datapath. The processor 20 may be a SIMD processor. The datapath 40 may communicate with the memory subsystem 30 via a bus.

An off-chip memory 80 may be provided off chip. The memory 80 may be shared memory, namely memory that is shared with other elements of an electronic device. As one example, the memory 80 may be memory for a digital video recorder (DVR).

The processor 20, such as the SIMD processor, may process data elements in parallel. For video and/or images, each element may correspond to one pixel to be displayed. Accordingly, the processor 20 may process pixels in parallel.

The datapath 40 may include a SIMD register file and/or a memory load/store unit. The memory load/store unit may provide load and store instructions to load and store ID row or 2D block of elements from the 2D array in the on-chip memory subsystem 30.

The on-chip memory subsystem 30 may provide the concept of 2D array storage (e.g. size 1024×512 elements) by enabling access to 1D row and 2D block of (more than N, e.g. N=16) elements in parallel in the 2D array.

The on-chip memory subsystem 30 may have a number of parallel memory banks with a number of data elements per addressable word of a memory bank.

The on-chip memory subsystem 30 may include a memory controller to service requests from the corresponding memory load/store unit, and to control reads from the parallel memory banks and writes to the parallel memory banks.

In at least one embodiment, an electronic apparatus may include a processor to perform an operation, and a memory subsystem 30 including a plurality of memory banks to store a 2D array of data using a shifted scheme. The memory subsystem may be on-chip with the processor.

As described hereinafter, the on-chip memory subsystem 30 may perform three primary features, namely to:

1) provide data to the datapath so as to keep the datapath (and bus) fully utilized. The provided data may be tailored to demands of target applications, and may minimize a number of memory accesses for SIMD implementations of processing tasks.

2) minimize a number of accesses to the off-chip memory 80 so as to limit interference with other concurrent contenders.

3) be efficient in silicon area and power dissipation terms.

The design of such a memory subsystem may be challenging, especially in view of versatility of applications' demands and need for ease of software development. Other arrangements may have addressed some of these requirements. The memory subsystems in other arrangements may range from general purpose to application-specific, with domain-specific memories in between the first two regarding application coverage. However, embodiments of the present invention may focus on memory subsystems for SIMD processors targeting video and image processing applications.

Embodiments may particularly relate to applications based on motion estimation and compensation and a broad class of finite impulse response (FIR) digital filters. One property of these applications may be a demand for storage of two-dimensional (2D) arrays of data elements and run-time defined accesses to groups of adjacent elements in 1D row, 1D column and 2D block shapes. For these desired shapes, two types of accesses may be demanded, aligned and unaligned. The aligned accesses may belong to a coarser grid (i.e., to a block of elements grid), whereas the unaligned accesses may be more flexible and belong to an element grid.

FIG. 2 shows a two-dimensional (2D) array of memory according to an example arrangement. Other arrangement may also be provided.

More specifically, FIG. 2 shows differently demanded ways to access data in video and image processing applications (i.e., access modes). The applications may process 2D arrays of data elements and demand accesses to 1D rows, 1D columns and 2D blocks of elements in the 2D arrays.

If the accessed 1D or 2D shape belongs to a coarser grid (e.g. 8*4 elements) the access may be aligned, and unaligned if it belongs to the element grid. In this illustration, the number of elements per 1D and 2D access is 8 and the 2D blocks are 4*2 (4 elements wide and 2 lines high) and 2*4, whereas in general these values may depend on the application.

To answer such demands, parallel memory subsystems that enable accesses to N elements in parallel may be applied in the N-way SIMD processors. The architecture spectrum may include monolithic parallel memory subsystems. The monolithic parallel memory subsystems may be based on an efficient configuration of memory banks (i.e., the number of memory banks, number of addressable words per bank and width of an addressable word). Such a strictly efficiency-driven design may enable only one access mode, which may be the aligned access to a 1D row of N elements. Other demanded access modes may have to be emulated in software, requiring multiple sequentially performed memory accesses and data shuffles in the datapath. This may limit the processing throughput to only a portion of bandwidth at which the memory subsystem provides data. In a balanced architecture, the processing throughput should be equal to the data bandwidth of the memory subsystem.

Multiple memory subsystems may enable unaligned accesses to 1D rows, 1D columns and 2D blocks of different aspect ratios (dimensions) that have N elements in total. These memory subsystems may contain N memory banks with one element per addressable word of a bank. To ensure that all elements of an arbitrarily positioned 1D or 2D shape may be accessed in parallel, specific schemes of storing data in the memory banks (i.e. storage schemes) may be used. These memory subsystems may hereafter be referred to as N-bank memory subsystems. For a large N, the N-bank memory subsystems may require a large number of memory banks (e.g. 16 or 32). This may result in a larger silicon area cost as compared to the monolithic subsystems. The larger cost may be acceptable for applications that need such flexible access modes. However, the N-bank subsystems may not enable a possibility for a trade-off between cost and flexibility according to the target application demands.

A two-level on-chip memory subsystem may address needs of the video post-processing domain. A first memory level, closest to the processor (such as the processor 20), may be based on less than N memory banks with multiple elements per addressable word of a bank. This memory level may enable unaligned read and aligned write of 2D blocks of N elements. The second memory level may keep the bandwidth towards the off-chip memory (such as the off-chip memory 80) close to a theoretical minimum of one access per element. However, for the two-level approach, a high bandwidth may be spent for transferring data between the two on-chip memory levels. This may reduce the data bandwidth available to the datapath and hence limit the processing throughput. Additionally, there may be two copies of the same elements in the on-chip memories, resulting in a less efficient use of the valuable on-chip storage space.

One property of these memory subsystems is parallel access of up to N elements. On the other hand, video and image processing algorithms may commonly need a group of N and several more adjacent input elements to produce N output elements. Examples of such algorithms may be linear and bilinear interpolation and FIR filters. With the memory subsystems that enable parallel access to N elements, SIMD implementations of these algorithms may perform two memory accesses to produce one output of N elements, such as shown in FIG. 3. In such cases, the processing throughput may be limited to one half of the data bandwidth provided by the memory subsystem, even if the datapath supports a higher throughput. If the memory subsystem enabled parallel access to N and several more elements, then only one memory access may be performed per one output of N elements. Therefore, such a memory subsystem may enable up to two times higher processing throughput.

FIG. 3(a) shows linear interpolation in a scalar way. FIG. 3(b) shows linear interpolation in a SIMD way.

In FIG. 3(a), two adjacent input elements (or pixels) P0 and P1 may be used to interpolate one output element P. In FIG. 3(b), to interpolate N=4 elements in parallel, a SIMD datapath may need N+1=5 adjacent input elements from the memory. For memory subsystems that enable a parallel read of N elements, two reads may be performed per N output elements. In contrast, if the memory subsystem enables a parallel read of one more than N elements, only one read may need to be performed.

Embodiments may provide a one-level memory subsystem that addresses requirements of video and image applications without drawbacks of other arrangements. To enable parallel access to more than N elements in a cost-efficient way, the memory subsystem 30 may contain less than N memory banks with multiple elements per a bank word, as discussed below in Section I(B). Such a configuration of memory banks may be combined with a storage scheme (discussed below in Section I(A)) to enable unaligned read and write accesses to 1D rows and 2D blocks.

The dimensions of the 2D block access may be configurable at runtime, as will be discussed below in Section I(C). In Section II(A), for each configuration of 2D block dimensions, a description may be provided of a total number of elements that may be accessed in parallel, which may be called parallelism of the memory subsystem. The parallelism and flexibility in configuring dimensions of the 2D block access may be determined by design-time parameters of the memory subsystem 30. The same parameters may also determine configuration of memory banks, and thereby costs in terms of silicon area and power dissipation, as will be described below in Section II(B).

The memory subsystem according to example embodiments may enable trade-offs between parallelism and flexibility on one side and costs on the other side. Advantages of the memory subsystem according to example embodiments may be provided in Section II(C) in comparison with the N-bank and two-level subsystems through a case study of motion estimation.

Section I Discussion of Memory Subsystem Architecture

A memory subsystem architecture according to an example embodiment may enable storage of 2D arrays of data elements and unaligned accesses to 1D rows and 2D blocks in the 2D arrays. To enable such access modes, the memory subsystem may contain multiple memory banks and may use a specific storage scheme.

A number of memory banks may be denoted as B, a number of addressable words per bank may be denoted as W, and a number of elements per addressable word of a bank may be denoted as E. The values of bank B, word W and element E may be determined at design-time based on input parameters of the memory subsystem, as will be described below in Section I(B).

In addition to a memory bank configuration, a specific storage scheme may be provided to ensure that all elements of a 1D row or a 2D block at an arbitrary position in the 2D array may be accessed in parallel. With the storage scheme, a set of rules (equations) may be provided that determine a unique location of each array element in the memory banks. The storage scheme, an analysis of its parallelism and equations may be provided in Section I(A).

Embodiments may provide a one-level memory with less than N parallel banks and multiple elements per addressable word of a bank (see equations 7-9 below), which in combination with a shifted storage scheme (see equation 4 below) may enable parallel access of more than N elements in 1D row and 2D block shapes to speed up SIMD video and image processing.

Embodiments may be provided where more than N elements may be loaded from the memory subsystem and passed to the SIMD processor with: (a) mostly standard SIMD instructions (that operate N elements in parallel); and (b) one or more specific SIMD instructions that has input of more than N elements and output of N elements (e.g. linear interpolation) to speed up SIMD video and image processing.

Embodiments may also use (or reuse) the parallel memory banks to enable lookup access with tradeoff between lookup speed and storage overhead.

Section I(A): Storage Scheme

Before describing the storage scheme according to an example embodiment of the memory subsystem, a simpler storage scheme according to an example arrangement may be described for a 2D array of A_(H) lines and A_(W) elements per line, as shown in FIG. 4(a). With the storage scheme according to the example arrangement, each line of the 2D array may be stored in the memory banks in a row-wise way beginning from the bank with index 0, as shown in FIG. 4(b).

FIG. 4(a) shows a 2D array of memory, and FIG. 4(b) shows parallel memory banks.

FIGS. 4(a)-4(b) show the scheme of storing a 2D array in parallel memory banks. Each array line is stored row-wise beginning from memory bank 0. The elements of each column of the array (e.g. M03, N03, P03 and R03), may be stored in different words of the same memory bank and can not be accessed in parallel assuming standard single-port banks. This scheme therefore does not enable 2D block accesses (e.g. M03, M04, N03 and N04), but only 1D row accesses (e.g. R05, R06, R07 and R08).

As an example, assume access to an element at a location (x, y) in the 2D array of FIG. 4(a), counted from a top-left array location (0, 0). To access the element, its location in the memory banks of FIG. 4(b) may have to be determined. The location in the memory banks may be determined based on three values, namely: (1) a bank index (Bank); (2) an addressable word in that bank (Word); and (3) an element position in the word (Elem). For the storage scheme according to an example arrangement, the following equations may determine these three values:

$\begin{matrix} {{{bank} = {\left\lfloor \frac{x}{E} \right\rfloor{mod}\mspace{14mu} B}}{{word} = {{y*\left\lceil \frac{A_{W}}{B*E} \right\rceil} + \left\lfloor \frac{x}{B*E} \right\rfloor}}{{elem} = {x{\;\mspace{11mu}}{mod}\mspace{14mu}{E.}}}} & (1) \end{matrix}$

The location (x, y) of an element in the 2D array (FIG. 4(a)) may also be expressed with a single value a, as a row-wise offset from the location (0, 0) to (x, y). In that example, a=y*A_(W)+x, y=la/A_(W)J and x=a mod A_(W). Considering that, the bank, word and elem equations may become:

$\begin{matrix} {{{bank} = {\left\lfloor \frac{a\mspace{20mu}{mod}\mspace{14mu} A_{W}}{E} \right\rfloor{mod}\mspace{14mu} B}}{{word} = {{\left\lfloor \frac{a}{A_{W}} \right\rfloor*\left\lfloor \frac{A_{W}}{B*E} \right\rfloor} + \left\lfloor \frac{a\mspace{20mu}{mod}\mspace{20mu} A_{W}}{B*E} \right\rfloor}}{{elem} = {\left( {a\mspace{14mu}{mod}\mspace{14mu} A_{W}} \right){mod}\mspace{14mu}{E.}}}} & (2) \end{matrix}$

An analysis may now relate to how many elements (or pixels) may be accessed in parallel with the storage scheme and in what shapes of elements may be accessed. With this scheme according to an example arrangement, all elements of a column of the 2D array may be located in different words of a same memory bank (e.g. M03, N03, P03 and R03 in FIG. 4(a)). Assuming that one word of a bank may be accessed at a time (i.e., single port banks), then only one element of a 2D array column may be accessed at a time. Therefore, the storage scheme according to the example arrangement may enable parallel access to only horizontally adjacent 2D array elements. In other words, the storage scheme according to the example arrangement may enable a 1D row access mode.

The number of elements that may be accessed in parallel may depend on access alignment (i.e., on a location of the most left element of the 1D row in the 2D array (a_(row))). If a_(row) is a multiple of E, then the access may be aligned to the memory bank grid. In that example, 1D row of B*E elements may be accessed. That is, a maximum number of elements may be accessible in parallel with this storage scheme and configuration of memory banks. However, parallelism of the scheme may be lower when the access is unaligned (i.e., when a_(row) is not a multiple of E). The number of elements that may be accessed in parallel may be minimal when a_(row)=k*E−1, k={1, 2, 3 . . . }. In these examples, the most left element of the accessed 1D row may be at the most right position in the memory bank word (e.g. M11 when a_(row)=11 in FIG. 4). In that bank, only one element may be accessed. At each of the remaining B−1 banks, E elements may be accessed in parallel. Therefore, the minimal number of horizontally adjacent elements of the 2D array that may be accessed in parallel is 1+(B−1)*E. This number of elements may be the guaranteed parallelism of the storage scheme according to the example arrangement, regardless of the 1D row access alignment.

To enable parallel access to a 2D block, the data has to be stored such that there are no two elements of the 2D block located in different words of a same memory bank. Embodiments of the memory subsystem may achieve this by using a shifted storage scheme as shown in FIG. 5.

FIG. 5 shows a shifted scheme of storing a 2D array in parallel memory banks according to an example embodiment. Other embodiments and configurations may also be provided.

With the shifted storage scheme, lines of the 2D array (FIG. 4(a)) may be stored row-wise in the memory banks (of FIG. 5), same as with the scheme of the arrangement discussed above with respect to FIG. 4(b). In contrast to the arrangement discussed above with respect to FIG. 4(b), adjacent lines of the 2D array (FIG. 4(a)) may be mutually shifted in the memory banks. More precisely, the n-th line of the 2D array may be stored beginning from the bank (n*S) mod B, where B is the number of banks, and S is a shift factor in terms of banks, and nε[0,A_(H)−1].

FIG. 5 shows B=4, S=2 and AH=4. Thereby every group of two adjacent array lines may be mutually shifted, and the scheme may enable accesses to 2D blocks of two lines in parallel. Additionally, the scheme may enable accesses to 1D rows in the same 2D array.

Assuming that the shift factor S divides the bank B, B/S adjacent lines of the 2D array may be mutually shifted in the memory banks. This may mean that 1D columns of B/S adjacent elements of the 2D array may be accessed in parallel. Since the shift between two adjacent array lines is S memory banks, parallel access to 1+(S−1)*E such 1D columns may be guaranteed regardless of the 2D block access alignment. In summary, the shifted storage scheme may enable access to an arbitrarily positioned 2D block of up to Blk_(H) lines with up to Blk_(W) elements per line, as defined by the following equations:

$\begin{matrix} {{{Blk}_{H} = \frac{B}{S}}{{Blk}_{W} = {1 + {\left( {S - 1} \right)*{E.}}}}} & (3) \end{matrix}$

In addition to accesses to such 2D blocks, the shifted scheme according to example embodiments may enable accesses to arbitrarily positioned 1D rows of up to 1+(B−1)*E elements in a same 2D array. That is because the elements of a 2D array line may be stored row-wise in the memory banks in the same way as with the above described scheme (FIG. 4(b)) according to an example arrangement. The possibility of both 1D row and 2D block accesses may be important since the 2D array elements may be transferred from the off-chip memory (such as the off-chip memory 80) as 1D rows, whereas the SIMD datapath may demand 2D block accesses.

The bank, word and elem equations that represent the shifted storage scheme may be defined by extending equation 2 with the shift factor S and the 2D block height Blk_(H):

$\begin{matrix} {\mspace{79mu}{{{bank} = {\left( {\left\lfloor \frac{a\mspace{14mu}{mod}\mspace{14mu} A_{W}}{E} \right\rfloor + {\left( {\left\lfloor \frac{a}{A_{W}} \right\rfloor{mod}\mspace{14mu}{Blk}_{H}} \right)*S}} \right){mod}\mspace{14mu} B}}{{word} = {{\left\lfloor \frac{a}{A_{W}} \right\rfloor*\left\lceil \frac{A_{W}}{B*E} \right\rceil} + {\left\lfloor \frac{\left\lfloor \frac{a\mspace{14mu}{mod}\mspace{14mu} A_{W}}{E} \right\rfloor + {\left( {\left\lfloor \frac{a}{A_{W}} \right\rfloor{mod}\mspace{14mu}{Blk}_{H}} \right)*S}}{B} \right\rfloor{mod}\left\lfloor \frac{A_{W}}{B*E} \right\rfloor}}}\mspace{79mu}{{elem} = {\left( {a\mspace{14mu}{mod}\mspace{14mu} A_{W}} \right){mod}\mspace{14mu}{E.}}}}} & (4) \end{matrix}$

Section I(B): Configuration of Parallel Memory Banks

The following may relate to a configuration of parallel memory banks. This may correspond to the on-chip memory subsystem 30 provided on chip.

As will be discussed, the parallel memory banks may include less than N memory banks and enable read/write of 2D blocks of data of N elements. The parallel memory banks may be considered a single level of memory, that has less than N memory banks, and access to more than N elements (in parallel). The processor may have access to more elements with less memory banks.

The equation 3 (discussed above) may related to (or define) parallelism of the shifted storage scheme. These equations may be analyzed to determine the value of the shift factor S, and the required memory banks configuration, namely bank B, element E and word W. These values may be determined for the given 2D block height Blk_(H) in terms of lines and block width Blk_(W) in terms of elements. Both the block height Blk_(H) and the block height Blk_(W) may be design-time parameters of the memory subsystem, such as the memory subsystem 30 shown in FIG. 1.

Assuming that the values of the bank B and the element E are fixed at design-time, by setting the value of the shift factor S, the storage scheme may be adjusted for different dimensions of 2D block accesses. The value of the shift factor S may also be fixed at design-time to enable simpler and faster hardware implementation of internal addressing logic defined by equation 4. One drawback may be a lack of flexibility to choose the 2D block dimensions at run-time. Another option may be to enable setting S at run-time to provide more flexibility of 2D block accesses.

This may result in a more complex and slower hardware implementation of the equations 4. One may enable setting the value of the shift factor S at run-time, but to limit it to powers of two. Accordingly, the run-time flexibility of 2D block accesses may be provided to a certain extent, as discussed in Section I(C), and complexity of hardware implementation may be kept moderate.

To further reduce complexity of hardware implementation, the values of B, E and A_(W) may be limited to powers of two. With these assumptions, all multiplication, division and modulo operations in the equations 4 may be implemented using only left shift, right shift and logical conjunction, respectively. Following the previous assumptions and considering the first equation in 3, the parameter block height Blk_(H) may need to be a power of two.

The third design-time parameter may be the number of elements processed in parallel by the target SIMD processor, denoted as N. The number of elements N may be assumed to be a power of two, which is the case for most of the SIMD processors.

Embodiments may enable parallel access to more than N elements when required by target applications. Two examples of the parameter block width Blk_(W) may be provided. In the first example, parallel access to more than N elements may be required. One additional column may be required per access to a 2D block with block height Blk_(H) lines (i.e. Blk_(W)=N/Blk_(H)+1). In the second example, a parallel access to N elements may be required and therefore Blk_(W)=N/Blk_(H). Considering these two examples and the second equation in 3, the following expressions may need to be true to guarantee a parallel access to a 2D block of Blk_(H) lines with Blk_(W) elements per line:

$\begin{matrix} {{{{1 + {\left( {S - 1} \right)*E}} \geq {\frac{N}{{Blk}_{H}} + 1}},{{Blk}_{W} = {\frac{N}{{Blk}_{H}} + 1}}}{{{1 + {\left( {S - 1} \right)*E}} \geq \frac{N}{{Blk}_{H}}},{{Blk}_{W} = {\frac{N}{{Blk}_{H}}.}}}} & (5) \end{matrix}$

Another concern of the design of the memory subsystem may be silicon area cost. Embodiments may use as few as possible memory banks. Following that and the first equation in 3, the shift factor S should be minimal for the given block height Blk_(H). The minimal values of the shift factor S such that the equations 5 have solutions

$\begin{matrix} {S_{\min} = \left\{ \begin{matrix} {2,} & {{Blk}_{W} = {{\frac{N}{{Blk}_{H}} + {1\bigvee{Blk}_{H}}} < N}} \\ {1,} & {{Blk}_{W} = {{\frac{N}{{Blk}_{H}}\bigwedge{Blk}_{H}} = {N.}}} \end{matrix} \right.} & (6) \end{matrix}$

Replacing the shift factor S with S_(min) in the first equation in 3 may provide the equations for the minimal required number of memory banks:

$\begin{matrix} {B = \left\{ \begin{matrix} {{2*{Blk}},} & {{Blk}_{W} = {{\frac{N}{{Blk}_{H}} + {1\bigvee{Blk}_{H}}} < N}} \\ {{Blk}_{H},} & {{Blk}_{W} = {{\frac{N}{{Blk}_{H}}\bigwedge{Blk}_{H}} = {N.}}} \end{matrix} \right.} & (7) \end{matrix}$

Considering the shift factor values provided by equation 6, the minimal power of two value of E may be provided such that the equations 5 are true.

$\begin{matrix} {E = {\frac{N}{{Blk}_{H}}.}} & (8) \end{matrix}$

To determine the number of addressable words of a memory bank W, the total capacity of the memory subsystem in terms of words of N elements may be assumed to be the fourth design-time parameter denoted with C. Assuming that C is even, the equations that determine W are:

$\begin{matrix} {W = {\frac{C*N}{B*E} = \left\{ \begin{matrix} {\frac{C}{2},} & {{Blk}_{W} = {{\frac{N}{{Blk}_{H}} - {1\bigvee{Blk}_{H}}} < N}} \\ {C,} & {{Blk}_{W} = {{\frac{N}{{Blk}_{H}}\bigwedge{Blk}_{H}} = {N.}}} \end{matrix} \right.}} & (9) \end{matrix}$

From the equations 6-9, the memory bank configuration of the N-bank memory subsystems may be equal to the configuration of the memory subsystem in the example of Blk_(H)=N and Blk_(W)=N/Blk_(H). The N-bank configuration may be considered as a special case of the memory banks configuration.

Section I(C): Run-Time Dimensions of 2D Block Access

This section may analyze flexibility in choosing dimensions of 2D block access at run-time, provided by the memory banks configuration and shifted storage scheme according to example embodiments. Other embodiments and configurations may also be provided.

It is assumed that a memory banks configuration may be determined at design-time according to equations 7-9. For the given memory banks configuration and according to equations 3, dimensions of 2D block access may be chosen at run-time by setting the value of the storage scheme shift factor S.

The equations 6 may define the minimal value of the shift factor needed to enable parallel access to an arbitrarily positioned 2D block of Blk_(H) lines with Blk_(W) elements per line. Increasing the value of the shift factor S may decrease the number of lines of a 2D block that may be accessed in parallel, but may increase the 2D block width as defined by the equations 3. The design-time parameter block height Blk_(H) may therefore represent the maximal number of lines of a 2D block that may be accessed in parallel. The number of lines of a 2D block that may be accessed in parallel may be minimal, and the 2D block width may be maximum in case of the maximal value of the shift factor S. The maximal value of the shift factor S is B memory banks, when the shifted storage scheme becomes equal to the scheme discussed above according to the example arrangement. The shift factor S may be set to any power of two between the minimal and maximal values. All values of the shift factor for the given configuration of memory banks are: S _(i) =S _(min)*2^(i) ,iε[0,log₂(Blk _(H))].  (10)

Each value of the shift factor Si may enable unaligned access to a 2D block of up to Blk_(Hi) lines and up to Blk_(Wi) elements per line, the values of Blk_(Hi) and Blk_(Wi) may be obtained by replacing the shift factor S with S_(i) in the equations 3:

$\begin{matrix} {{{Blk}_{Hi} - \frac{B}{S_{i}} - \frac{B}{S_{\min}*2^{i}} - \frac{{Blk}_{H}}{2^{i}}}{{Blk}_{Wi} - 1 + {\left( {S_{i} - 1} \right)*E} - 1 + {\left( {{S_{\min}*2^{i}} - 1} \right)*{\frac{N}{{Blk}_{H}}.}}}} & (11) \end{matrix}$

According to the set of values of I given by the equation 10, the number of 2D block dimensions supported with one memory banks configuration may be proportional to Blk_(H). Therefore, the parameter Blk_(H) may determine the run-time flexibility in choosing the 2D block access dimensions.

Section II Results

A. Parallelism Analysis

The parallelism P_(i) may be analyzed of the presented memory subsystem, defined as the number of elements that may be accessed in parallel. In an example of a 2D block access of Blk_(Hi) lines and Blk_(Wi) elements per line, the parallelism is P_(i)=Blk_(Hi)*Blk_(Wi) elements. Considering that and the equations 11 and 6, the following equation may be derived:

$\begin{matrix} {P_{i} = \left\{ \begin{matrix} {\frac{{N*\left( {2^{i + 1} - 1} \right)} + {Blk}_{H}}{2^{i}},} & {{Blk}_{W} = {\frac{N}{{Blk}_{H}} + {1\bigvee}}} \\ \; & {{BLk}_{H} < N} \\ {N,} & {{Blk}_{W} = {{\frac{N}{{Blk}_{H}}\bigwedge{Blk}_{H}} = {N.}}} \end{matrix} \right.} & (12) \end{matrix}$

P_(i) may now be compared with the parallelism of the memory subsystems that enable parallel access to N elements. The parallelism advantage of the presented memory subsystem may be calculated as the number of elements that may be accessed in parallel in addition to N:M_(i)=P_(i)−N. By replacing P_(i) with the right side of the equation 12, the following result may be obtained:

$\begin{matrix} {M_{i} = \left\{ \begin{matrix} {\frac{{N*\left( {2^{i + 1} - 1} \right)} + {Blk}_{H}}{2^{i}},} & {{Blk}_{W} = {\frac{N}{{Blk}_{H}} - {1\bigvee}}} \\ \; & {{BLk}_{H} < N} \\ {0,} & {{Blk}_{W} = {{\frac{N}{{Blk}_{H}}\bigwedge{Blk}_{H}} = {N.}}} \end{matrix} \right.} & (13) \end{matrix}$

In the examples of Blk_(W)=N/Blk_(H)+1 or Blk_(H)<N, M_(i) is greater than zero and monotonically increases as i increases from 0 to log 2(Blk_(H)). The minimum of M_(i) is Blk_(H) for i=0 (i.e., for a 2D block access of Blk_(H) lines and N/Blk_(H)+1 elements per line). The maximum of M_(i) is (N/Blk_(H))*(Blk_(H)−1)+1 for i=log 2(Blk_(H)) (i.e., for a 2D block access of one line). The guaranteed parallelism of the presented memory subsystem may therefore N+Blk_(H) elements, regardless of the 2D block access dimensions.

In the example of Blk_(W)=N/Blk_(H) and Blk_(H)=N, the presented memory subsystem may be equal to the N-bank subsystems, as discussed in Section I(B). In that example, there is no parallelism advantage of the presented memory subsystem.

Table I illustrates P_(i) and M_(i) defined by equations 12 and 13, respectively, for values of the design-time parameters N and Blk_(H), and for Blk_(W)=N/Blk_(H)+1.

Considering the equations 12 and 13, as well as Table I, for a given N, the parallelism of the presented memory subsystem may be proportional to Blk_(H)

TABLE 1 PARALLELISM OF THE PRESENTED MEMORY SUBSYSTEM, GIVEN FOR VALUES OF THE DESIGN-TIME PARAMETERS N AND Blk_(H). N DENOTES THE NUMBER OF ELEMENTS PROCESSED IN PARALLEL BY THE TARGET SIMD PROCESSOR. Blk_(H) DENOTES THE MAXIMAL NUMBER OF LINES ACCESSIBLE IN THE MEMORY SUBSYSTEM IN CASE OF 2D BLOCK ACCESS MODE. AS THE TOTAL NUMBER OF ELEMENTS THAT CAN BE ACCESSED IN PARALLEL (P_(i)) DEPENDS ON THE RUN-TIME DIMENSIONS OF 2D BLOCK ACCESS, THE MINIMUM AND MAXIMUM OF P_(i) ARE GIVEN FOR EACH PAIR OF N AND Blk_(H). THE PARALLELISM ADVANTAGE OF THE PRESENTED OVER OTHER SUBSYSTEMS THAT ENABLE PARALLEL ACCESS TO N ELEMENTS IS M_(i) = P_(i) − N. M_(i) IS GIVEN BOTH IN TERMS OF ELEMENTS AND PERCENTAGE (Mi = N * 100). WE CAN NOTICE THAT P_(i) AND M_(i) INCREASE AS Blk_(H) INCREASES, FOR EACH GIVEN N. N Blk_(H) P_(i) M_(i) elements lines elements elements % 16 2 18-25 2-9  13-56 16 4 20-29 4-13 25-81 16 8 24-31 8-15 50-94 32 2 34-49 2-17  6-53 32 4 36-57 4-25 13-78 32 8 40-61 8-29 25-91

B. Silicon Area and Power Dissipation Costs

Silicon area and power dissipation costs of the presented memory subsystem may now be analyzed. The costs of a memory subsystem may include the memory banks costs and costs of the subsystem's internal logic that may control the banks and implement specific access modes. The banks costs may be dominant over the logic costs, which may be confirmed in Section II(C). Therefore, only the memory banks costs may be discussed.

For a given configuration of memory banks, the total silicon area may be a simple sum of areas of B memory banks. The silicon area cost may therefore be determined at design-time, along with the configuration of memory banks.

The total power dissipation may depend on a frequency of performing memory accesses at run-time, as well as on the number of banks that are active while performing an access. In this section, it is assumed that one million memory accesses per second (i.e., the access frequency of one megahertz (MHz)). It may be assumed that the maximal number of elements per access is defined by equation 12, which requires activating all memory banks. Following these assumptions, the total power dissipation may be the sum of dissipations of B individual banks, and may represent the maximal dissipation of a given memory banks configuration. In Section II(B)1, power dissipation may be analyzed in examples when the number of elements per memory access is lower than the maximum.

FIG. 6 are graphs showing silicon area and maximal power dissipation costs. Other graphs and configurations may also be provided. FIG. 6 illustrates the silicon area and power dissipation costs for values of N and Blk_(H), for Blk_(W)=N/Blk_(H)+1, and multiple representative cases of total subsystem capacity. The costs in a low power 65 nm CMOS technology may be provided for values of the design-time parameters N and Blk_(H), as well as for multiple values of total capacity of the memory subsystem in terms of kilobytes (KB). N may denote the number of elements processed in parallel by the target SIMD processor. Blk_(H) may denote the maximal number of lines accessible in the memory subsystem in case of 2D block access mode. The data element may be 8 bits wide. The charts may indicate that silicon area and power dissipation may moderately increase as Blk_(H) doubles, which is the case for all shown combinations of N and the total capacity. For comparison, the charts may show the costs of the N-bank configurations that contain N memory banks with one 8 bit element per addressable word and the same total capacity as the corresponding presented configuration.

Additionally, a data element may be assumed to be 8 bits wide, which may be needed to determine width of the banks in terms of bits (8*E). The illustrated costs may be based on single port SRAM (Static Random Access Memory) banks in a low power 65 nm CMOS technology.

FIG. 6 shows that the silicon area and power dissipation costs of the presented memory subsystem may increase as the Blk_(H) increases. The flexibility in choosing 2D block dimensions at run-time and the parallelism of the memory subsystem are also proportional to Blk_(H), as discussed in Sections II(C) and III(A), respectively. The presented memory subsystem may enable trade-offs between the flexibility and parallelism on one side and the costs on the other side.

FIG. 6 also shows costs of the N-bank configuration of memory banks for the same values of N, total capacity and data element width. If we compare the costs of the presented memory subsystem to the N-bank costs, we can observe the following.

The silicon area of the presented memory subsystem may be lower in almost all illustrated examples. In these examples, the silicon area advantage of the presented memory subsystem may be up to 25%. The exceptions may be the examples when the value of Blk_(H) is high (8), the total capacity is small (16 KB and 32 KB) and N=16. In these two examples, the silicon area overhead of the presented memory subsystem may be 3-8%. However, as Table I indicates, such silicon area overhead may be justified by 50-94% higher access parallelism.

The power dissipation of the presented memory subsystem may be lower in most examples. The exceptions are the examples when Blk_(H) is high (8) or the total capacity is 16 KB. In these examples, the power dissipation of the presented memory subsystem may be higher by 5-25%, whereas the parallelism may be higher by 25-94%.

To conclude, compared to the N-bank subsystems, the presented memory subsystem may offer advantages in both parallelism and costs. In the great majority of other examples, the silicon area and power dissipation overheads may be justified by at least two times higher advantage in the parallelism. In the worst case for the presented memory subsystem (i.e., N=16 and the total capacity of 16 KB), the parallelism advantage may be equal to the power dissipation overhead.

1) Power Dissipation Analysis:

Earlier in Section II(B), the maximal power dissipation of the presented memory subsystem was analyzed, assuming the maximal number of elements per 2D block access, as defined by equation 12. The maximal number of elements per access may be greater than N with configurations of the memory subsystem such that Blk_(W)=N/Blk_(H)+1 or Blk_(H)<N.

In addition to the 2D block access modes of more than N elements, the same memory subsystem configurations may provide access modes of N elements. These access modes may be provided to increase run-time flexibility of the memory subsystem, and support a wider range of applications.

The 2D block access modes of N elements may be defined to access the same number of lines as defined by equation 11. Following that the number of elements per line may be lower such that the number of elements per 2D block is N:

$\begin{matrix} {{{Blk}_{Hi}^{N} - {Blk}_{Hi} - \frac{{Blk}_{H}}{2^{i}}}{{Blk}_{Wi}^{N} = {\frac{N}{{Blk}_{Hi}^{N}} = {2^{i}*{\frac{N}{{Blk}_{H}}.}}}}} & (14) \end{matrix}$

In this section, power dissipation may be analyzed when the 2D block accesses of N elements are performed. In the analysis, a memory bank may be assumed to dissipate power only when it is active. In other words, power dissipation of a memory bank may be neglected when the bank is not active and its input pins are held stable. This assumption may be true with the low power 65 nm CMOS technology. The power dissipation of a 2D block access may therefore be proportional to the number of memory banks that are activated to access all elements of the 2D block.

In case a 2D block access is aligned to the bank grid (i.e., the 2D block address is a multiple of E elements), the number of activated memory banks may be (Blk_(Wi) ^(N)/E)*Blk_(Hi) ^(N). Otherwise, in case of an unaligned 2D block access, one additional memory bank may be activated per line of the 2D block. The total number of activated memory banks in this example is therefore (Blk_(Wi) ^(N)/E)+1)*Blk_(Hi) ^(N).

If we assume a large number of 2D block accesses at runtime defined (pseudo-random) addresses, in average there may be 1/E*100% bank aligned and (E−1)/E*100% unaligned accesses. The average number of activated banks for a 2D block access of Blk_(Hi) ^(N) lines and Blk_(Wi) ^(N) elements per line is:

$\begin{matrix} {B_{i}^{a} = {{{\frac{1}{E}*\frac{{Blk}_{Wi}^{N}}{E}*{Blk}_{Hi}^{N}} + {\frac{E - 1}{E}*\left( {\frac{{Blk}_{Wi}^{N}}{E} + 1} \right)*{Blk}_{Hi}^{N}}} = {{Blk}_{H} + {\left( {1 - \frac{{Blk}_{H}}{N}} \right)*{{Blk}_{Hi}^{N}.}}}}} & (15) \end{matrix}$

By multiplying B_(i) ^(α) with the power dissipation of a single memory bank, we may obtain the average power dissipation per 2D block access of N elements. Following that and analyzing equation 15, we may conclude the following. In examples of the N-bank configuration of memory banks (Blk_(H)=N), the average power dissipation may be determined at design-time by the parameter N, and may be constant regardless of the runtime choice of 2D block access dimensions. In examples when Blk_(H)<N, the average power dissipation may be determined by the design-time parameters Blk_(H) and N, as well as by the run-time chosen number of lines Blk_(Hi) ^(N) of the accessed 2D block. In other words, besides the design-time trade-off, there may be a run-time trade-off between the number of lines of a 2D block access of N elements and the average power dissipation. FIG. 7 illustrates these trade-offs for values of N and Blk_(H), and all values of Blk_(Hi) ^(N) defined by equation 14.

Average power dissipation in case of 2D block accesses of N elements and the presented configurations of memory banks that enable parallel access to more than N elements. The power dissipation values in a low power 65 nm CMOS technology may be provided for multiple memory banks configurations, determined by values of the design-time parameters N and Blk_(H). For each design-time configuration, the power dissipation may be provided for all dimensions of 2D block access that may be chosen at run-time. N may denote the number of elements processed in parallel by the target SIMD processor. Blk_(H) may denote the maximal number of lines accessible in the memory subsystem in an example of 2D block access mode. Blk_(Hi) ^(N) may denote the run-time chosen number of lines of a 2D block

C. Motion Estimation Case Study

This section may provide a case study of motion estimation to illustrate advantages of the presented memory subsystem in comparison with a selected N-bank and two-level subsystems. The used motion estimation algorithm may be briefly described in Section III(C1), and details of the compared memory subsystems may be provided in Section III(C2). In Section III(C3), the number of memory accesses needed for SIMD implementation of the motion estimation may be analyzed, and thus the maximal processing throughput enabled by each of the compared subsystems. To verify the analytical analysis and conclusions, the experimental results may be provided in Section III(C4).

1) Motion Estimation Algorithm:

Motion estimation may be an important tasks in many video and image applications, such as video frame-rate conversion, video codecs, video and image stabilization and image denoising. To compare the memory subsystems, a 3-D recursive search (3DRS) block-matching algorithm may be used.

The input of this algorithm may be a sequence of luma frames of a video, where each frame may consist of 8 bit data elements (i.e., the luma component of Y′C_(b)Cr pixels representation). These frames may be processed one by one, and for each processed frame (current) one additional frame (reference) may be used. The current frame may be split into blocks of 8*8 elements, and for each block one motion vector may be chosen out of 7 candidate vectors. To choose the best candidate, the currently processed block from the current frame may be compared for similarity to the 7 reference blocks pointed by the candidate vectors in the reference frame. As the measure of similarity of two compared blocks, the sum of their absolute differences (SAD) may be calculated. Since the algorithm uses quarter-pel accurate vectors to increase overall accuracy of motion estimation, the candidate vectors may point between elements of the reference frame. Therefore, elements of the reference blocks used in SAD calculations may be bilinearly interpolated from the elements at neighboring full-pel positions in the reference frame. The summary of the algorithm may be provided in Table II.

2) Compared Memory Subsystems:

An implementation of the described motion estimation algorithm using the two-level memory subsystem may have been reported. The processing throughput per square millimeter of silicon area may be eight times greater than the previous state-of-the-art. Therefore, we may use the two-level subsystem and the reported results in the comparison.

TABLE II THE BLOCK-MATCHING MOTION ESTIMATION ALGORITHM USED IN THE CASE STUDY. THIS ALGORITHM USES THE SUM OF ABSOLUTE DIFFERENCES (SAD) AS A MEASURE OF SIMILARITY OF TWO 8 * 8 BLOCKS IN THE BLOCK-MATCHING PROCESS. IT EVALUATES 7 CANDIDATE MOTION VECTORS PER BLOCK, BY CALCULATING 7 SAD VALUES BETWEEN THE CURRENTLY PROCESSED BLOCK AND EACH OF THE REFERENCE BLOCKS POINTED BY THE CANDIDATE VECTORS. SINCE THE CANDIDATE VECTORS ARE QUARTER-PEL ACCURATE, THE REFERENCE BLOCKS ARE BILINEARLY INTERPOLATED. IN THIS CASE STUDY THE RESOLUTION OF INPUT VIDEO IS 1920 * 1080 ELEMENTS, AND THE CANDIDATE VECTORS ARE LIMITED WITHIN THE SEARCH AREA OF 224 * 96 ELEMENTS, CENTERED AT THE CURRENTLY PROCESSED BLOCK. Block size (elements * lines) 8 * 8 Blocks similarity measure SAD Candidate vectors per block 7 Accuracy of motion vectors quarter-pel Interpolation of reference blocks bilinear Video resolution (elements * lines) 1920 * 1080 Search area size (elements * lines) 224 * 96 

To represent the N-bank memory subsystems in the comparison, we choose a M_(R) subsystem. This memory subsystem may be chosen from among the other N-bank subsystems since this memory subsystem may provide the most suitable access modes for implementation of the motion estimation algorithm, and its internal logic may be the least costly in terms of silicon area.

In case of the memory subsystem, the configuration that enables unaligned access to a 2D block of 9*2 elements may be chosen, which may be suitable for bilinear interpolations of 8*8 reference blocks followed by SAD calculations. Table III may provide details of the compared subsystems.

3) Analysis of Memory Accesses:

The number of memory accesses that need to be performed for one SAD calculation with each of the memory subsystems may be analyzed. To perform an SAD calculation, the current and the reference 8*8 blocks may be needed. The current block may be read from the memory subsystem once per 7 SAD calculations. To read the current block 8*8:N:7=0.6 memory accesses may be performed per SAD calculation. This number may be the same for all three memory subsystems. In case of the two-level subsystem, these accesses may be performed in the second memory level (L1), the one farther from the datapath.

TABLE III THE DETAILS OF THE MEMORY SUBSYSTEMS COMPARED IN THE MOTION ESTIMATION CASE STUDY. N DENOTES THE NUMBER OF ELEMENTS PROCESSED IN PARALLEL BY THE TARGET SIMD PROCESSOR. Blk_(H) IS A DESIGN-TIME PARAMETER OF THE SUBSYSTEM PRESENTED IN THIS WORK, AND DENOTES THE MAXIMAL NUMBER OF LINES ACCESSIBLE IN THE SUBSYSTEM IN CASE OF 2D BLOCK ACCESS MODE. Blk_(W) IS ANOTHER DESIGN-TIME PARAMETER OF THE PRESENTED SUBSYSTEM, AND DENOTES THE MAXIMAL NUMBER OF ELEMENTS PER LINE IN CASE OF A 2D BLOCK ACCESS OF Blk_(H) LINES. IN THE CASE STUDY, Blk_(W) IS SET TO N/Blk_(H) + 1 TO ENABLE UNALIGNED ACCESS TO A 9 * 2 2D BLOCK. THEREBY, A BILINEAR INTERPOLATION OF AN 8 * 8 BLOCK CAN BE IMPLEMENTED WITH 5 9*2 MEMORY ACCESSES. THAT IS SIGNIFICANTLY FEWER THAN 10 AND 9 ACCESSES NEEDED WITH THE 8 * 2 AND 4 * 4 ACCESS MODES OF THE COMPARED TWO-LEVEL AND N-BANK SUBSYSTEMS, RESPECTIVELY. THE TOTAL CAPACITIES OF THE SUBSYSTEMS ARE GIVEN IN TERMS OF KILOBYTES (KB). This work Two-level N-bank N (elements) 16 16 16 Blk_(H) (lines) 4 — — Blk_(W) (elements) 5 — — Access modes 4 * 4, 8 * 2, 4 * 4, 8 * 2, 4 * 4, (elements * lines) 9 * 2, 16 * 1 16 * 1 16 * 1 Element width (bits) 8 8 8 Total capacity (KB) 128 120 128

On the other hand, the reference blocks used in SAD calculations may be bilinearly interpolated. For a bilinear interpolation of an 8*8 block, 9*9 neighboring elements may read from the memory subsystem. For the two-level subsystem implementation, 8*2 access mode may have been used, which may imply 10 memory accesses per SAD calculation. These accesses may be performed in the first memory level (L0), which is the closest to the datapath. In case of the N-bank subsystem, 9 4*4 memory accesses may be performed per SAD calculation. In case of the presented memory subsystem and 9*2 access mode, 5 memory accesses may be performed per SAD calculation.

Beside those reads from the on-chip memory subsystem, there may be writes performed to transfer parts of the current and reference frames from the off-chip memory. We may assume the minimal bandwidth to the off-chip memory of one access per element. Therefore, there may 2*8*8:N:7=1.1 writes per SAD calculation. In an example of the two-level subsystem, these writes may be performed in the L1 memory level.

In the example of the two-level subsystem, additional memory accesses may be performed to transfer the part of the reference frame between the on-chip memory levels (from L1 to L0). The number of reads from the L1 and writes to the L0 memory may depend on the vertical search area in terms of 8*8 blocks, as well as on the order of processing the blocks of a frame. The reported implementation based on the two-level subsystem may have the vertical search area of 96:8=12 blocks, and the block processing order may be a 2-meander. Therefore, there are 8*8*(12+2):N:7:2=4 accesses to both L0 and L1 memories per SAD calculation.

The total number of memory accesses per SAD calculation in examples of the presented and the N-bank subsystems is 6.7 and 10.7, respectively. In case of the L0 and the L1 memories of the two-level subsystem, the total number of accesses is 14 and 5.7, respectively. As expected, the higher number of accesses may be performed in the L0 memory. The overall throughput of the two-level subsystem based implementation may therefore be determined by 14 accesses per SAD calculation.

By considering the number of memory accesses per SAD calculation, the presented memory subsystem may enable 1.6 and 2.1 times higher processing throughput than the N-bank and the two-level subsystems, respectively.

4) Experimental Results:

To verify cost-efficient realizability of the concepts presented in Section II, the presented memory subsystem may have been implemented. The subsystem has been implemented as a configurable module in a hardware description language, functionally verified and productized. To get the silicon area of the internal logic and memory banks of the presented memory subsystem, the module configuration specified in Table III may have been synthesized in the low power 65 nm CMOS technology. According to the synthesis results, the internal logic may represent less than 5% of the total silicon area of the subsystem. Compared to the total silicon area of other configurations in FIG. 6, the internal logic may be between 3% for the largest and 13% for the smallest total capacity of the memory subsystem. Therefore, the memory banks costs may be dominant over the logic costs, as assumed in Section III(B).

To measure the processing throughput in terms of frames per second (fps), the motion estimation program for a processor consisting of the presented memory subsystem and an 8-issue Very Long Instruction Word (VLIW) datapath may have been developed. Out of 8 VLIW issue slots, 4 may be with SIMD and 4 may be with scalar functional units. The same datapath may have been previously used for implementation of the motion estimator based on the two-level subsystem. To compile and schedule the developed program, a Silicon Hive ANSI-C compiler may be used. To run the program and measure the processing throughput, the cycle-accurate Silicon Hive Multi-processor simulator may have been used. Based on the memory accesses performed at the program run-time, used access modes and alignment of addresses, power dissipation of the memory subsystem may be calculated in terms of milliwatts (mW). The bandwidth to the off-chip memory in terms of accesses per element of the processed video frames may have been calculated in the same way. The results obtained in this way may be summarized in the column “This work” of Table IV.

For comparison, the column “Two-level” of Table IV may include results of the two-level subsystem based implementation.

The motion estimation program for a processor may be developed based on the N-bank configuration of the presented memory subsystem (Blk_(H)=16 and Blk_(W)=1). The processor datapath may have been the same as used for the implementations with the presented and two-level subsystems. The 4*4 access mode for interpolation of the reference blocks may be used to precisely reflect the most efficient implementation with the compared N-bank subsystem. The processing throughput, power dissipation and off-chip bandwidth may have been obtained in the same way as in the example of the presented memory subsystem. These results may be shown in the column “N-bank” of Table IV.

TABLE IV THE RESULTS OF THE MOTION ESTIMATION IMPLEMENTATION BASED ON THE MEMORY SUBSYSTEM PRESENTED IN THIS WORK AND A VLIW AND SIMD DATAPATH. FOR COMPARISON, THE RESULTS OF THE IMPLEMENTATIONS BASED ON THE SELECTED REFERENCE TWO-LEVEL AND N-BANK SUBSYSTEMS ARE SHOWN. ALL THREE IMPLEMENTATIONS USE THE SAME MOTION ESTIMATION ALGORITHM AND THE SAME DATAPATH. THE FIRST PART SHOWS SILICON AREA COSTS OF THE MEMORY BANKS AND INTERNAL LOGIC IN THE LOW POWER 65 NM CMOS TECHNOLOGY. THE SECOND PART SHOWS THE THROUGHPUT IN TERMS OF THE PROCESSED 1920 * 1080 FRAMES PER SECOND (FPS) ACHIEVED WITH THE CLOCK FREQUENCY OF 250 MHz, AS WELL AS THE POWER DISSIPATION OF EACH SUBSYSTEM FOR THAT THROUGHPUT. THE BANDWIDTH TO THE OFF-CHIP MEMORY IS GIVEN IN TERMS OF ACCESSES PER ELEMENT OF PROCESSED FRAMES. FINALLY, THE MEASURE OF EFFICIENCY OF EACH SUBSYSTEM IS CALCULATED AS THE PRODUCT OF ALL COSTS (SILICON AREA, POWER DISSIPATION AND OFF-CHIP BANDWIDTH) DIVIDED BY THE ACHIEVED THROUGHPUT. ACCORDING TO THE NORMALIZED VALUES OF THIS MEASURE, THE PRESENTED MEMORY SUBSYSTEM IS 2.6 AND 2.9 TIMES MORE EFFIENT THAN THE TWO-LEVEL AND N-BANK SUBSYSTEMS, RESPECTIVELY. 8-issue VLIW @ 250 MHz (4 SIMD + 4 scalar issue slots) Processor datapath This work Two-level N-bank Memory subsystem Silicon area (nm²) Memory banks 0.7563 0.7478 0.8967 Logic 0.0365 0.0287 0.0083 Total 0.7928 0.7765 0.9050 Logic/Total 4.6% 3.7% 0.9% Throughput (fps) 101 60 71 Dissipation (mW) 19.33 26.49 34.51 Off-chip bandwidth 1.12 1.29 1.12 (accesses/element) Costs/Throughput 1 2.6 2.9

As a measure of the memory subsystem efficiency, the product of the costs (i.e., the silicon area, power dissipation and off-chip bandwidth), may be calculated and divided the product by the processing throughput. For each memory subsystem, the calculated value may be normalized by dividing it with the efficiency measure of the presented memory subsystem. The memory subsystem may be more efficient when the value calculated in this way is smaller.

The results of this case study may show that the presented memory subsystem is 2.6 and 2.9 times more efficient than the two-level and N-bank subsystems, respectively. With the presented memory subsystem, 1.7 and 1.4 times higher processing throughput may have achieved. The achieved throughput may be 10-20% less than the maximum enabled by the memory subsystem, determined in Section III(C3). By optimizing the processor datapath for the presented memory subsystem, the maximal processing throughput can be achieved.

The throughput achieved with the presented memory subsystem may be higher by 41 fps compared to the two-level subsystem case. There may be two main differences between these memory subsystems that enable the higher throughput, the number of levels in the on-chip memory hierarchy and the 9*2 access mode. The N-bank subsystem may be in between, since it may have one memory level as the presented subsystem and enable the same access modes as the two-level subsystem. By comparing the throughputs of the N-bank and two-level subsystem exampled, it may be determined that having one instead of two on-chip memory levels may increase the throughput by 11 fps. Using the 9*2 access mode in case of the presented subsystem results in the additional 30 fps.

Rather than increasing the number of frames processed per second, the throughput headroom enabled by the presented memory subsystem may be used in other ways. For example, more sophisticated motion estimation with up to 12 candidate vectors per 8*8 block may be performed with the throughput of 60 fps. Another possibility may be to increase the video resolution to approximately 2560*1440 and achieve the 60 fps throughput.

As assumed in Section III(C3), the off-chip bandwidth may be close to the theoretical minimum of one access per element in all compared cases. With the presented and N-bank subsystems, the off-chip bandwidth may be lower by 13% than with the two-level subsystem. The reason for the difference may be a smaller capacity and less efficient use of the on-chip storage space in case of the two-level subsystem, due to two copies of elements of the reference frames in the subsystem.

Section IV Conclusions

Embodiments may provide a parallel memory subsystem for SIMD processors targeting video and image processing applications. The memory subsystem may enable on-chip storage of 2D arrays of video and image data elements, and unaligned accesses to 1D rows and 2D blocks of elements.

The memory subsystem may be configurable at design-time and at run-time. The design-time parameters may determine parallelism of the subsystem and its flexibility in terms of supported dimensions of 2D block access. At run-time, one of the supported dimensions may be chosen and used for accessing the 2D array. Concurrently with the chosen 2D block, the memory subsystem may enable 1D row accesses in the same array, which may be commonly required for efficient data transfers between the off-chip memory and the on-chip memory.

Silicon area and power dissipation costs of the memory subsystem may be proportional to its parallelism and flexibility. This may provide a full spectrum of trade-off possibilities according to specifics of target applications. Compared to the selected reference subsystems, configurations of the presented memory subsystem may enable 13-25% higher parallelism with lower or similar costs. The configurations that enable higher parallelism advantage (e.g. 50%) may be more power-costly than the reference memory subsystems, but the power overhead may be more than 2 times lower than the parallelism advantage.

Advantages of the presented memory subsystem may have been analytically and experimentally illustrated through implementation of a block-matching motion estimation algorithm. The motion estimator based on the presented memory subsystem may process 40-70% more frames per second and the memory subsystem may dissipate 27-44% less power. The silicon area of the presented memory subsystem may be similar to the smallest area of the reference subsystems. The bandwidth towards the off-chip memory may be equal to the smallest bandwidth of the reference subsystems (i.e., 1.12 accesses per element of processed frames). Considering the number of frames processed per second divided by the product of the three implementation costs, the presented memory subsystem may be 2.6-2.9 times more efficient than the reference subsystems.

Higher efficiency of the memory subsystem may be achieved due to better tailored access modes to the application needs, which may reduce the number of accesses per processed frame by 1.6-2.1 times. The same approach may be used to accelerate other video and image applications with specific memory access needs.

Section V Further Embodiment

Embodiments may provide an approach to enable fast vector lookup access to a vector scratchpad memory, which may be needed in modern image and video processing applications. A vector scratchpad memory may relate to SIMD processing. In other words, a vector may correspond to SIMD, and scratchpad memory may correspond to cache memory.

The vector lookup access may enable speeding up applications such as image enhancement, object detection and tracking, and high dynamic range imaging (HDR). The presented vector lookup access mode may be a part of vector memory of a SIMD processor, such as the processor 20 of FIG. 1) of a camera subsystem of a chip.

Section V(A): Problem Statement and Previous Solution

A Look-Up Table (LUT) data structure may be an array of values of a mathematical function, provided for a limited number of arguments values. The LUTs may replace slower run-time computations of function values by faster indexing the array. The function values may be pre-computed (at compile time or at the beginning of the program execution) and stored to the LUT in the memory (such as the memory subsystem 30). A read from the LUT (i.e. a lookup) may be a memory access to the address corresponding to the specified table index. If a memory access is faster than computation of the function value, then the program execution may also be faster. The LUTs may be widely used in signal processing, computer graphics and multimedia application domains

To enable implementation of LUT based applications on the SIMD processors, a vector lookup access mode to the LUT may be used. An example of an N-wide SIMD processor, an argument of a vector lookup access may be a vector of N table indices, and a result may be a vector of N LUT values corresponding to the specified indices. A simple and cost-efficient way to implement the vector lookup access may be by performing N successive reads from the scalar data memory that contains the LUT, and reading one LUT value per memory access. Latency of such a vector lookup access may be at least N clock cycles, which may be too slow for some (real-time) applications. To enable vector lookup access in a single clock cycle, a memory architecture may be used that consists of N memory banks, where one LUT value may be stored at one addressable word of a memory bank. The LUT may be replicated N times and each replica may be stored in one memory bank, thus enabling lookup access to N independently addressed LUT values at a time. However, this solution may be be costly in terms of silicon area when the number of memory banks is large. Moreover, there may be an overhead in storage space proportional to N, since there are N replicas of each LUT value stored in the memory.

Embodiments may provide an approach to enable vector lookup access by reusing a plurality of memory banks of the presented memory subsystem (or the vector scratchpad memory architecture) disclosed above. Since the memory banks may be completely reused, the vector lookup access may be enabled without additional cost in terms of silicon area of the memory banks. Moreover, embodiments may enable a full spectrum of design-time and run-time trade-offs between the vector lookup access latency (speed) and the storage space overhead.

Section V(B): Solution Approach

The memory subsystem (or the vector scratchpad memory architecture) may contain B memory banks of W addressable words and E elements per addressable word, and may enable element aligned access to 1D vectors and 2D blocks of elements. The values of B, W and E may be determined by the three design-time parameters according to the equations 16.1, 16.2 and 16.3, respectively. The first design-time parameter N may be a number of elements in a vector of the SIMD processor. The second parameter C may be a capacity of the memory in terms of vectors. The third parameter Blk_(Hmax) may be a maximum height (in terms of lines) of an element aligned 2D block of elements that may be accessed in the vector memory. As described above, the parameters N and Blk_(Hmax) are powers of two, while C is an even number.

$\begin{matrix} {B = \left\{ \begin{matrix} {{2*{Blk}_{Hmax}},} & {{Blk}_{Hmax} < N} \\ {{Blk}_{Hmax},} & {{Blk}_{Hmax} = N} \end{matrix} \right.} & (16.1) \\ {W = \left\{ \begin{matrix} {\frac{C}{2},} & {{Blk}_{Hmax} < N} \\ {C,} & {{Blk}_{Hmax} = N} \end{matrix} \right.} & (16.2) \\ {E = \frac{N}{{Blk}_{Hmax}}} & (16.3) \end{matrix}$

Section V(C): Concept of Vector Lookup Access

The B memory banks of the described (vector) memory architecture may be used for storing B replicas of a LUT, as shown in FIG. 8, and thus enable reading B independently addressed LUT values at a time. A vector lookup access may be performed in N/B clock cycles. A LUT value may be stored in all B memory banks, while a word of a memory bank may contain E consecutive LUT values.

FIG. 8(a) shows a LUT of 16 values of a function ƒ(x) for the argument values xε[0, 15]. FIG. 8 (b) shows the LUT is stored to 8 memory banks of 2 elements (LUT values) per addressable word. This method of storing the LUT in the memory banks may enable accessing 8 LUT values at a time. Hence, a vector lookup access of N=8 LUT values may be performed in N/8 clock cycles. The LUT may occupy 8 addressable words in each memory bank.

The location of a LUT value ƒ(x) in each memory bank may be determined by the word address word_(x) and the element position elem_(x) within the word, as follows.

$\begin{matrix} {{{word}_{x} = \left\lfloor \frac{x}{E} \right\rfloor}{{elem}_{x} = {x\mspace{14mu}{mod}\mspace{14mu} E}}} & (16.4) \end{matrix}$

If the table index x is located at the position p within the input vector of N table indices, the LUT value ƒ(x) may be read from the memory bank bank_(p) in the clock cycle cycle_(p) relative to the beginning of the vector lookup access.

$\begin{matrix} {{{bank}_{p} = {p\mspace{14mu}{mod}\mspace{14mu} B}}{{cycle}_{p} = \left\lfloor \frac{p}{B} \right\rfloor}{p \in \left\lbrack {0,{N - 1}} \right\rbrack}} & (16.5) \end{matrix}$

Having B LUT replicas stored in the memory banks may enable the fastest vector lookup access in an example of the proposed architecture with B memory banks. However, the storage space overhead may also be maximal in this example, since each LUT value may be stored in all memory banks. Hence, up to W*E LUT values may be stored in the memory, which is B times less than the memory capacity in terms of elements.

Section V(D): Enabling the Trade-Off Between Vector Lookup Access Latency and Storage Space Overhead

There may be R LUT replicas stored in the memory banks (R≦B). With R LUT replicas, B memory banks may be grouped in R groups of B/R memory banks per group, and each LUT replica may be stored in a different group of memory banks.

FIG. 9 shows four LUT replicas (R=4) of 16 values stored in 4 groups of 2 memory banks per group. In this example, 4 LUT values may be be accessed at a time. A vector lookup access of N=8 LUT values may be performed in N/R=2 clock cycles. The LUT may occupy 4 addressable words in each memory bank.

The number of LUT replicas may be a divisor of the number of memory banks, which is a power of two according to the equation 16.1. Therefore, R may be chosen according to the following equation. R=2^(j) ,jε[0,log₂(B)]  (16.6)

In example of R LUT replicas stored in the memory banks, the equations word_(x), elem_(x), bank_(x,p) and cycle_(p) may as follows.

$\begin{matrix} {{{word}_{x} = \left\lfloor \frac{x}{E*\frac{B}{R}} \right\rfloor}{{elem}_{x} = {x\mspace{14mu}{mod}\mspace{14mu} E}}{{bank}_{x,p} = {\left\lfloor \frac{x\mspace{14mu}{mod}\mspace{14mu}\left( {E*\frac{B}{R}} \right)}{E} \right\rfloor + {\left( {p\mspace{14mu}{mod}\mspace{14mu} R} \right)*\frac{B}{R}}}}{{cycle}_{p} = \left\lfloor \frac{p}{R} \right\rfloor}{p \in \left\lbrack {0,{N - 1}} \right\rbrack}} & (16.7) \end{matrix}$

Having R LUT replicas stored in the memory banks may enable reading R LUT values at a time, and thus a vector lookup access may be performed in N/R clock cycles. The maximum size of a LUT that may be stored in the memory is W*E*(B/R) values. Accordingly, the storage space overhead may decrease and the latency vector lookup access may increase, as the number of the LUT replicas is becoming lower. Therefore, by choosing the number of LUT replicas at design-time or run-time, a trade-off may occur between the vector lookup access latency and the storage space overhead. With such a trade-off enabled, the vector memory may be better adjusted to the target application requirements.

Section V(E): Writing a LUT to the Memory

Writing the LUT to the memory may be performed only once, at the beginning of a program execution. Writing the LUT may not be critical for performance and may be performed by using vector aligned writes of 1D vectors of N elements, as illustrated in

FIG. 10 shows writing a vector of N=8 LUT values to the memory banks. In this example, E*(B/R)=4 consecutive LUT values may be replicated N/(E*(B/R))=2 times and copied to the vector. The vector may then be written R/(N/(E*(B/R)))=2 times to the memory banks to write the 4 different LUT values to all R=4 groups of memory banks.

The addressing equations discussed above as well as the addressing circuitry may be reused.

The content of a vector to be written to the LUT in the vector memory may be prepared in the following way. Namely, min(N,E*(B/R)) consecutive LUT values may be replicated max(1,N/(E*(B/R))) times and copied to the vector. The vector may then be written R/max(1,N/(E*(B/R))) times to the memory to write the LUT values to all R groups of the memory banks (LUT replicas).

Section V(F): Application of the Further Embodiment

Embodiments of the vector scratchpad memory and the described vector lookup access mode may be applied in any SIMD processor. It may be suitable in an example of processors designed for low power, cost sensitive and real-time applications in domains of signal processing, computer graphics and multimedia. The proposed vector lookup access mode may be applied in the vector scratchpad memory of a camera subsystem of a chip.

Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments.

Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art. 

What is claimed is:
 1. An electronic apparatus comprising: a processor to perform an operation; and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme between different banks of the plurality of parallel memory banks, and each memory bank to include at least two elements per bank word, each memory bank to include a plurality of addressable words per bank, and each word of a specific one of the plurality of banks to include a plurality of elements, wherein the shifted scheme includes the memory subsystem to store data from adjacent lines of the 2D array by shifting a second line of data relative to a first line of data such that data of the second line of data is provided within different ones of the plurality of memory banks, and wherein based on the shifted second line of data to different ones of the plurality of memory banks no two elements of a 2D block from the 2D array are located in different words of a same memory bank.
 2. The electronic apparatus of claim 1, wherein the memory subsystem to store data from adjacent lines of the 2D array by shifting a storage location of one adjacent line of data.
 3. The electronic apparatus of claim 1, wherein the plurality of parallel memory banks to include less than N memory banks, and a memory controller to provide a read or write of 2D blocks of N elements.
 4. The electronic apparatus of claim 1, wherein the memory subsystem is a one level memory subsystem.
 5. The electronic apparatus of claim 1, wherein the processor is a single-instruction-multiple data processor.
 6. The electronic apparatus of claim 1, wherein the processor to receive N data elements in parallel from the memory subsystem.
 7. The electronic apparatus of claim 1, wherein the memory subsystem is provided on-chip with the processor.
 8. The electronic apparatus of claim 1, wherein the processor to perform motion estimation and compensation based on data within the plurality of parallel memory banks.
 9. The electronic apparatus of claim 1, wherein the processor to perform features relating to a finite impulse response (FIR) digital filter.
 10. The electronic apparatus of claim 1, wherein the processor to perform video and image processing applications based on data within the plurality of parallel memory banks.
 11. The electronic apparatus of claim 1, wherein the memory subsystem to provide unaligned access to one dimensional (1D) rows and two dimensional (2D) blocks of elements.
 12. An electronic apparatus comprising: a processor; and a memory subsystem that includes a plurality of parallel memory banks to store data representing a two-dimensional (2D) array of data, and the 2D array to be accessed with a selected 2D block and to be stored in the plurality of parallel memory banks, each memory bank to include a plurality of addressable words per bank, each word of a specific one of the plurality of banks to include a plurality of elements, wherein the memory subsystem to store data from adjacent lines of the 2D array by shifting a second line of data relative to a first line of data such that data of the second line of data is provided within different ones of the plurality of memory banks, and wherein based on the shifted second line of data to different ones of the plurality of memory banks no two elements of a 2D block from the 2D array are located in different words of a same memory bank.
 13. The electronic apparatus of claim 12, wherein the memory subsystem to store data from adjacent lines of the 2D array by shifting a storage location of one adjacent line of data.
 14. The electronic apparatus of claim 12, wherein each memory bank to include multiple elements per bank word.
 15. The electronic apparatus of claim 12, wherein the memory subsystem is a one level memory subsystem.
 16. The electronic apparatus of claim 12, wherein the processor is a single-instruction-multiple data processor.
 17. The electronic apparatus of claim 12, wherein the processor to receive N data elements in parallel from the memory subsystem.
 18. The electronic apparatus of claim 12, wherein the memory subsystem is provided on-chip with the processor.
 19. The electronic apparatus of claim 12, wherein the memory subsystem to provide unaligned access to one dimensional (1D) rows and two dimensional (2D) blocks of elements.
 20. The electronic apparatus of claim 12, wherein the plurality of parallel memory banks to include less than N memory banks, and a memory controller to provide a read or write of 2D blocks of N elements. 